Occlusion Culling and Hardware Accelerated Volume Rendering

Abstract

Within this dissertation, a set of algorithmic optimizations are developed, enabling significant performance improvements due to a much better utilization of the available bandwidth. Additionally, new architectural concepts circumventing the bottle-necks of currently available general purpose graphics hardware are presented. In the field of polygon rendering, a unique mechanism for hardware supported occlusion queries to cull geometry prior to geometry transformation --- saving bandwidth on the front bus --- is presented. As an orthogonal addition to this, a novel visibility driven rasterization scheme is presented, saving processing cycles within the pipeline by culling occluded geometry prior to rasterization. Thus, more objects can be rendered or more cycles can be spent on multi-pass rendering of the potentially visible objects. With respect to volume rendering, this dissertation contributes the first side by side comparison of different volume rendering algorithms identifying each algorithm's strengths and weaknesses. Furthermore, new techniques for using polygon graphics hardware and multi-pass rendering are presented, enabling the combination of shading and classification of volume data. Additionally, minor modifications to the data path are proposed such that multi-pass rendering can be avoided, thus increasing the overall achievable frame-rate. Furthermore, we demonstrate how to efficiently use general purpose hardware (a single-chip SIMD architecture) for volume rendering, providing much more flexibility than dedicated polygon graphics hardware. As a summary of the above described work, a novel low-cost special purpose hardware architecture that achieves superior image quality while providing an incomparable degree of flexibility is presented.

Within this dissertation, a set of algorithmic optimizations are developed, enabling significant performance improvements due to a much better utilization of the available bandwidth. Additionally, new architectural concepts circumventing the bottle-necks of currently available general purpose graphics hardware are presented. In the field of polygon rendering, a unique mechanism for hardware supported occlusion queries to cull geometry prior to geometry transformation --- saving bandwidth on the front bus --- is presented. As an orthogonal addition to this, a novel visibility driven rasterization scheme is presented, saving processing cycles within the pipeline by culling occluded geometry prior to rasterization. Thus, more objects can be rendered or more cycles can be spent on multi-pass rendering of the potentially visible objects. With respect to volume rendering, this dissertation contributes the first side by side comparison of different volume rendering algorithms identifying each algorithm's strengths and weaknesses. Furthermore, new techniques for using polygon graphics hardware and multi-pass rendering are presented, enabling the combination of shading and classification of volume data. Additionally, minor modifications to the data path are proposed such that multi-pass rendering can be avoided, thus increasing the overall achievable frame-rate. Furthermore, we demonstrate how to efficiently use general purpose hardware (a single-chip SIMD architecture) for volume rendering, providing much more flexibility than dedicated polygon graphics hardware. As a summary of the above described work, a novel low-cost special purpose hardware architecture that achieves superior image quality while providing an incomparable degree of flexibility is presented.