Development Activities of the Frame Processor for the Athena WFI Instrument

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Zitierfähiger Link (URI): http://hdl.handle.net/10900/182132
http://nbn-resolving.org/urn:nbn:de:bsz:21-dspace-1821320
Dokumentart: Dissertation
Erscheinungsdatum: 2026-08-07
Sprache: Englisch
Fakultät: 7 Mathematisch-Naturwissenschaftliche Fakultät
Fachbereich: Physik
Gutachter: Santangelo, Andrea (Prof. Dott.)
Tag der mündl. Prüfung: 2026-07-22
DDC-Klassifikation: 530 - Physik
Freie Schlagwörter:
Digital Electronics
Athena
X-ray Astronomy
High-Energy Astrophysics
Lizenz: http://tobias-lib.uni-tuebingen.de/doku/lic_ohne_pod.php?la=de http://tobias-lib.uni-tuebingen.de/doku/lic_ohne_pod.php?la=en
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Abstract:

Athena is the next generation X-ray observatory to be launched by the European Space Agency (ESA), bringing several innovations and higher performance than any previous X-ray mission. Two main instruments will be flying on board Athena: the X-ray Integral Field Unit (X-IFU) and the Wide Field Imager (WFI). The first consists of a microcalorimeter instrument based on transition edge sensor technology, and the second one consists of state-of-the-art DEPFET sensors providing unprecedented energy resolution and high-speed readout capabilities. The focus of this work lies on the WFI instrument, specifically on the design and development of the frame pre- processing pipeline, which is a fundamental element of the WFI’s detector electronics subsystem. The unprecedented high-count rate capabilities of the WFI instrument imply that an enormous amount of data is produced during WFI observations. This precious data far surpasses the current bandwidth capabilities of modern spacecraft systems, creating the necessity of on-board data screening and preprocessing, downloading then only the scientifically relevant X-ray data to the ground. A demonstrator model of the WFI frame processor has been designed, developed, and manufactured, demonstrating successfully the technological capability of processing on-board in real-time the WFI data utilizing a pipeline concept in a single space qualified FPGA device. This thesis focuses on the description of such pipelines, outlining the design challenges, and concluding by providing the verification and validation results obtained during the frame processor demonstrator model development.

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